View SOC-3000_3669207.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

july 2002 document order number: SOC-3000-0001-sp SOC-3000/i scale-on-chip ? asic technical specification rev.b1
? 2001 cybratech (1998) ltd. all rights reserved. cybratech (1998) ltd. reserves the right to alter the equipment specifications and descriptions in this publication without prior notice. no part of this publication shall be deemed to be part of any contract or warranty unless specifically incorporated by reference into such contract or warranty. the information contained herein is merely descriptive in nature, and does not constitute a binding offer for the sale of the product described herein.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page i july, 2002 table of contents list of figures ................................................................................................................ .................. iv list of tables ................................................................................................................. .....................v general ........................................................................................................................ ............................1 g eneral d escription ............................................................................................................................2 a dvantages ............................................................................................................................... .............2 specifications................................................................................................................. .....................3 a nalog - to -d igital c onverter (adc)...............................................................................................3 adc converter main channel ? wheatstone bridge (load cell)........................................................3 adc converter auxiliary channel ................................................................................................ .......3 r eference i nputs ............................................................................................................................... ....4 d igital i nput ............................................................................................................................... ...........4 d igital o utput ............................................................................................................................... ........4 f lash m emory ............................................................................................................................... .........4 cpu ............................................................................................................................ ...............................5 f requency s ource i nput ......................................................................................................................5 p ower s upply and m onitor .................................................................................................................5 e nvironmental c onditions .................................................................................................................5 a bsolute m aximum r ating * ...............................................................................................................6 o utline d imensions ............................................................................................................................... 6 s cale m ain b oard l ayout a nd a ssembly p rocess p arameters f or SOC-3000........................7 pin configuration .............................................................................................................. ...............9 cpu 80c51tbo ................................................................................................................... ......................21 m emory o rganization .......................................................................................................................22 flash (program & non-volatile data) memory mapping and usage ...............................................22 application program start address .............................................................................................. ......23 serial downloading (in-circuit programming)..................................................................................23 using the flash for data memory ................................................................................................ ......24 data memory mapping ............................................................................................................ ...........25 memory bank select register .................................................................................................... .........25 cpu sfrs and configuration registers (cfr)..................................................................................25 i nstruction s et ............................................................................................................................... .....25 r eset ............................................................................................................................... .......................26 i nterrupt v ectors ..............................................................................................................................2 6 adc controller interface ....................................................................................................... 27 c ontroller r egisters ........................................................................................................................27 semaphore register............................................................................................................. ................27 control register ............................................................................................................... ...................27
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page ii july, 2002 status/data registers .......................................................................................................... ................28 o peration ............................................................................................................................... ...............29 keyboard controller............................................................................................................ ..... 31 c ontroller r egisters ........................................................................................................................32 r egisters d escription .........................................................................................................................32 control register ............................................................................................................... ...................32 data registers ................................................................................................................. ....................32 o peration ............................................................................................................................... ...............33 lcd controller/driver .......................................................................................................... .... 35 lcd bias generator............................................................................................................. ...............36 drive mode waveforms........................................................................................................... ............36 r egisters d escription .........................................................................................................................42 control register ............................................................................................................... ...................42 data registers ................................................................................................................. ....................43 o peration ............................................................................................................................... ...............44 led parallel display controller ...................................................................................... 45 r egisters d escription .........................................................................................................................46 semaphore register............................................................................................................. ................47 data registers ................................................................................................................. ....................47 o peration ............................................................................................................................... ...............48 led serial interface display controller..................................................................... 49 r egisters d escription .........................................................................................................................50 control register ............................................................................................................... ...................51 semaphore register............................................................................................................. ................51 data registers ................................................................................................................. ....................52 o peration ............................................................................................................................... ...............53 programmable frequency controller.......................................................................... 55 o peration ............................................................................................................................... ...............56 c ontrol r egisters d escription ........................................................................................................56 watchdog timer................................................................................................................. ............. 57 o peration ............................................................................................................................... ...............57 c ontrol r egisters d escription ........................................................................................................57 low voltage detector ........................................................................................................... .... 59 i nterrupt r egister ..............................................................................................................................5 9 configuration registers (cfr)............................................................................................... 61 special function registers (sfr) .......................................................................................... 65 g lobal c onfiguration r egister ......................................................................................................65 operation...................................................................................................................... .......................65 c ontrollers c lock e nable r egister ..............................................................................................66 c ontrollers reset r egisters .........................................................................................................67
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page iii july, 2002 i/o operation.................................................................................................................. .....................69 8051-compatible on-chip peripherals..................................................................................71 p arallel i/o p orts ..............................................................................................................................7 1 timers/counters................................................................................................................ ..................71 SOC-3000 initialization ........................................................................................................ ..........73 SOC-3000 hardware design considerations and peripheral interface connections .................................................................................................................... ....................75 l oad c ell i nterface ...........................................................................................................................75 4-wire and 6-wire interfaces................................................................................................... ...........75 load cells connected in parallel ............................................................................................... ........77 load cell impedance ............................................................................................................ ..............78 k eyboard i nterface ...........................................................................................................................78 lcd d isplay i nterface ......................................................................................................................79 led d isplay i nterface .......................................................................................................................80 e xternal i nterrupt s ources ............................................................................................................80 using the vdet input:.......................................................................................................... .................80 using timer0 and timer1 inputs: ................................................................................................ .......81 i 2 c-c ompatible i nterface ..................................................................................................................81 p ower s aving s chemes .......................................................................................................................81 g rounding and b oard l ayout r ecommendations .......................................................................82 in-circuit emulator (ice) system ..........................................................................................83 examples of pin configuration programming ............................................................85 e xample 1: c onfiguring a 20- digit lcd d isplay and an 8 x 8 k eyboard ...................................85 e xample 2: c onfiguring a 16- digit lcd d isplay , an 8 x 4 k eyboard , 8 o utput and 4 i/o p orts ............................................................................................................................... .......................86 e xample 3: c onfiguring a 21- digit led p arallel d isplay , an 8 x 8 k eyboard and 13 o utput p orts ............................................................................................................................... .........87 e xample 4: o utputs and i/o p orts p rogramming .........................................................................88
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page iv july, 2002 list of figures f igure 1: SOC-3000 t ypical a pplication ........................................................................................ 1 f igure 2: SOC-3000 b lock d iagram ................................................................................................. 2 f igure 3: m echanical o utline d rawing ........................................................................................ 6 f igure 4: m ain b oard pad s d imensions r ecommendation ........................................................ 7 f igure 5: SOC-3000 p in a rrangement ........................................................................................... 15 f igure 6: SOC-3000 lcd d isplay p in c onfiguration ................................................................. 16 f igure 7: SOC-3000 led d isplay p in c onfiguration ................................................................. 17 f igure 8: cpu b lock d iagram ........................................................................................................ 21 f igure 9: SOC-3000 p rogram m emory m ap .................................................................................. 22 f igure 10: SOC-3000/i s tartup p rocedure .................................................................................... 24 f igure 11: SOC-3000 d ata m emory m ap ......................................................................................... 25 f igure 12: k eyboard m atrix c onfiguration ................................................................................ 31 f igure 13: lcd c ontroller /d river b lock d iagram ................................................................... 35 f igure 14: s tatic d rive m ode w aveforms ..................................................................................... 37 f igure 15: 1:2 m ultiplex d rive r atio ?1/2 b ias w aveforms ....................................................... 38 f igure 16: 1:2 m ultiplex d rive r atio ?1/3 b ias w aveforms ....................................................... 39 f igure 17: 1:3 m ultiplex d rive r atio w aveforms ....................................................................... 40 f igure 18: 1:4 m ultiplex d rive r atio w aveforms ....................................................................... 41 f igure 19: b ackplane o utputs per lcd d igit ............................................................................... 43 f igure 20: led p arallel d isplay c ontroller b lock d iagram ................................................ 45 f igure 21: led p arallel d isplay c ontroller t iming d iagram ............................................... 46 f igure 22: led s erial i nterface d isplay b lock d iagram ......................................................... 49 f igure 23: led s erial i nterface c ontroller t iming d iagram ................................................. 50 f igure 24: c lock g enerator b lock d iagram ............................................................................... 55 f igure 25: l ow v oltage d etector .................................................................................................. 59 f igure 26: 4-w ire l oad -c ell c onnection ...................................................................................... 76 f igure 27: 6-w ire l oad -c ell c onnection ...................................................................................... 76 f igure 28: m ultiple l oad -c ell c onnection .................................................................................. 77 f igure 29: k eyboard i nterface ....................................................................................................... 78 f igure 30: lcd d isplay i nterface ................................................................................................... 79 f igure 31: led p arallel d isplay i nterface ................................................................................. 80
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page v july, 2002 list of tables t able 1: SOC-3000 p in c onfiguration for lcd d isplay .................................................................9 t able 2: SOC-3000 p in c onfiguration for led d isplay ...............................................................12 t able 3: n otes on SOC-3000 p in c onfiguration .............................................................................15 t able 4: SOC-3000 q uick r eference p in c onfiguration for lcd d isplay ...............................18 t able 5: SOC-3000 q uick r eference p in c onfiguration for led d isplay ...............................19 t able 6: i nterrupt v ectors d escription .........................................................................................26 t able 7: adc c ontroller r egisters d escription .........................................................................27 t able 8: adc c ontroller i nterface s emaphore r egister b it d efinitions .............................27 t able 9: adc c ontroller i nterface c ontrol r egister b it f unctions ....................................28 t able 10: adc c ontroller i nterface d ata r egister b it d efinitions ....................................28 t able 11: adc c ontroller i nterface d ata r egister b it f unctions ......................................28 t able 12: adc o utput c ounts v s . adc s ettings ......................................................................30 t able 13: k eyboard c ontroller r egisters d escription ...........................................................32 t able 14: k eyboard c ontroller c ontrol r egister b it f unctions .........................................32 t able 15: k eyboard c ontroller d ata r egister b it d efinitions .............................................33 t able 16: m aximum d isplay c apacity per d isplay c onfiguration ..........................................36 t able 17: lcd b ias c onfigurations ...............................................................................................36 t able 18: lcd c ontroller /d river r egisters d escription ........................................................42 t able 19: lcd c ontroller c ontrol r egister b it f unctions ...................................................42 t able 20: lcd c ontroller d ata r egister b it d efinitions ? 20-d igit d isplay ......................43 t able 21: led p arallel d isplay c ontroller d river r egisters d escription .......................46 t able 22: led p arallel d isplay c ontroller s emaphore r egister b it d efinitions ............47 t able 23: led p arallel d isplay c ontroller s emaphore r egister b it f unctions ..............47 t able 24: led p arallel c ontroller d ata r egister b it d efinitions ......................................47 t able 25: led s erial c ontroller d river r egisters d escription ............................................50 t able 26: led s erial i nterface d isplay c ontrol r egister b it f unctions ...........................51 t able 27: led s erial i nterface d isplay d ata r egister b it d efinitions ................................52 t able 28: c lock f requency c ontrol r egister b it s ettings .....................................................56 t able 29: w atchdog t imer o perating p arameters ....................................................................57 t able 30: w atchdog t imer c ommand s equence ..........................................................................57 t able 31: p ower -f ailure i nterrupt r egister b it s ettings .......................................................59 t able 32: cfr b it a ssignment .........................................................................................................62 t able 33: g lobal cfr r egister .......................................................................................................65 t able 34: c lock e nable r egister ...................................................................................................66 t able 35: c ontrollers c lock e nable r egister b it f unctions .................................................67 t able 36: c ontrollers reset r egister ........................................................................................67 t able 37: b it -o riented i/o p orts a ddresses , p in and b it a ssignment ....................................69 t able 38: b yte -o riented o utput p orts a ddresses and p in a ssignment ................................69 t able 39: a vailable p ins on the 80c51 i/o p ort ..........................................................................71 t able 40: i 2 c-c ompatible i nterface h ardware i nterface .......................................................81 t able 41: e xample 1: 20-d igit lcd d isplay , 88 k eyboard ......................................................85 t able 42: e xample 2: 16-d igit lcd d isplay , 84 k eyboard , 8 o utput , 4 i/o..........................86 t able 43: e xample 3: 21-d igit led d isplay , 88 k eyboard , 13 o utput ..................................87 t able 44: o utput and i/o p orts p rogramming .............................................................................88

cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 1 july, 2002 g eneral features scale-on-chip system ? single-chip scale electronics ? full oiml r-76 compliance SOC-3000 - 3000 d SOC-3000i - 6000 d ? up to eight load cells ? 6-wire load cell connection (including sense inputs) peripherals ? supports lcd and led displays: lcd: up to 20 digits (160 segments, 440) led: up to 24 digits ? keyboard: up to 64 keys ? serial communication: rs-232/485 ? i/o (set-points): up to 40 lines ? temperature sensor input cpu ? enhanced 80c51tbo ? 4 cycles/instruction ? 120kbyte, field-programmable flash program and data memory ? 4kbyte ram ? 4kbyte non-volatile data flash analog?to?digital converter ? resolution-20 bits ? sample rate-5, 10, 20 samples per second ? programmable gain-0.5, 0.75, 1, 1.5, 2 power ? 5/3.3v operation, 15ma ? battery operation support ? power failure detector applications ? price computing scales ? weighing indicators ? counting scales ? checkout scales SOC-3000 8 . . . . . 888 sen? sig+ sen+ s 0-39 sig? lcd (20 digits) led (21 digits) led/lcd module bp 0-3 buzzer load cell (up to 8) v in v inp 5v + 3.3v txd rxd i/o set point rs-232 printer rs-485 8 kb 1-8 kbi 1-8 up to 64 keys +5v f igure 1: SOC-3000 t ypical a pplication
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 2 july, 2002 general description the SOC-3000 asic is an 84-pin, single-chip scale intended to replace present-day, multiple-component weighing scale electronic circuitry designs. it includes the pre-amplifier, adc converter, display drivers, keyboard controller, serial communication, embedded cpu and field-programmable program and data memory. as a "stand-alone" unit it incorporates all scale hardware functions and represents a true breakthrough in scale manufacturing. it eliminates the risks, costs and inventory needs associated with discrete components. the SOC-3000 comes with a comprehensive software library, which implements hardware drivers, such as the display and keyboard, as well as most of the standard weighing functions. a complete development environment is available, enabling youto tailor and customize the application according to specific needs. the general SOC-3000 block diagram is presented in figure 2. advantages ? generic oiml r-76 approval ? minimize hardware and software development ? significantly cuts time-to-market ? reduces inventory needs mux delta - sigma adc 20 bits microcontroller core and peripherals 80c51tbo 120kx8 program/data flash 4k x 8 ram watchdog timer 3x16-bit timers power supply monitor i2c compatible spi like serial interfaces uart display controllers / drivers lcd / led 20 - 24 digits keyboard controller 8 x 8 internal bandgap reference power-down detector frequency controller 8 8 8 . . . . serial communication i/o keyboard load cell aux. channel oscillator/ resonator display ref+ ref- vdet pga f igure 2: SOC-3000 b lock d iagram
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 3 july, 2002 s pecifications analog-to-digital converter (adc) adc converter main channel ? wheatstone bridge (load cell) parameter min typ max unit comments differential input voltage 0 +10 mv programmable gain 0.5 2 up to 8 load cell offset drift vs. temperature 20 ppm/oc gain drift vs. temperature 4 ppm/oc integral non-linearity 0.004 % of full scale common-mode rejection (cmr) 120 db power supply rejection 120 db output noise 200 nvp-t-p 1 count resolution 20 bit sample rate 5 10 20 samples/s adc converter auxiliary channel parameter min typ max unit comments analog input voltage 0 0.8 v offset drift 20 ppm/oc gain drift 4 ppm/oc resolution 20 bit sample rate 5 10 20 samples/s
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 4 july, 2002 reference inputs parameter min typ max unit comments reference input 5 v ratiometric digital input parameter min typ max unit comments v ih (input high voltage) 2 5 v ttl level excluding xtal v il (input low voltage) 0.0 0.8 v ttl level excluding xtal xtal input v ih (input high voltage) v il (input low voltage) 2.5 0.4 v v v dd = 3.3v v dd = 3.3v digital output for lcd display mode: parameter min typ max unit comments v oh (output high voltage) 5 v lcd output set by user by external resistors v ol (output low voltage) 0.0 v lcd v lcd output set by user by external resistors for i/o mode: parameter min typ max unit comments v oh (output high voltage) 3.3 v v ol (output low voltage) 0.0 0.8 v flash memory parameter min typ max unit endurance 10,000 100,000 cycles data retention 100 years erase full memory single block (4kbyte) 100 25 ms ms program byte 20 us
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 5 july, 2002 cpu parameter min typ max unit comments enhanced 80c51tbo reset signal threshold start-up time ? from power on ? from idle mode ? from power down from watchdog reset 500 1 1 500 1 3.98 v ms ms ms ms ms oscillator power-down not through oscen bit. oscillator power-down through oscen bit. frequency source input parameter min typ max unit comments frequency level 16 mhz crystal oscillator or resonator power supply and monitor parameter min typ max unit comments input voltage monitor 4.50 4.75 v power fail input monitor level 2.21 v set by external resistors analog voltage input (av cc ) 4.75 5.00 5.25 v digital voltage input (v cc ) 3.00 3.30 3.60 v power supply current (i in ) cpu freq. = 16 mhz cpu freq. = 8 mhz cpu freq. = 4 mhz cpu freq. = 2 mhz cpu freq. = 1 mhz cpu freq. = 0.5 mhz 21 15 12 11 10 10 ma ma ma ma ma ma 5v and 3.3v . without connected i/o ports all controllers operating. depends on the software program and the flash memory utilization. environmental conditions parameter min typ max unit comments -10 20 40 oc full performance temperature -20 20 70 oc operation humidity 0 95 % non-condensing
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 6 july, 2002 absolute maximum rating* parameter min typ max unit comments av cc 6 v analog power v dd 4 v digital power v cc 6 v power input signal voltage 3.6 v operating temperature ?20 +70 oc storage temperature ?20 +85 oc lead temperature manual soldering reflow soldering 300 225 oc oc soldering for 10 seconds 60 seconds * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. the functional operation of the device under these or any other conditions outside of the range listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect the reliability of the device. outline dimensions the outline dimensions of the SOC-3000 plcc-84 case is shown in figure 3. pin 1 0.045 (1.143) x 45o indicates relative locations of pin 1 1.150 (29.20) 1.158 (29.41) sq. 1.185 (30.09) 1.155 (30.35) sq. f igure 3: m echanical o utline d rawing
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 7 july, 2002 scale main board layout and assembly process parameters for SOC-3000 1. pad definition will be according to figure 4. 2. solder mask opening should be 3mil (total 6 mil). 3. board finish may be hal (hot air leveling), immersion gold over nickel or immersion. 4. verify that the SOC-3000 components are packaged in hermetically sealed package. if the packaging is damaged or has been opened, perform the following drying procedure to assure that SOC-3000 components are completely dry: ? components drying procedure: place the SOC-3000 components in their tray and put them into a baking oven to dry at a temperature of 105oc for a minimum of 6 hours. 5. reflow temperature profile should be set according to the paste parameters. 6. maximum reflow temperature should be less than 225 oc. 7. recommended paste: koki, aim, multicore a. type 3 b. nc c. rma or equivalent f igure 4: pcb b oard l ayout (dimensions are in milli inches (mil))

cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 9 july, 2002 p in c onfiguration the SOC-3000 pin configuration for lcd and led displays is presented in table 1 and table 2, respectively, followed by a glossary of terms used in the tables. general notes on SOC-3000 pin configuration are presented in table 3, page 15. the physical pin arrangement is shown in figure 5, page 15. the physical pin configuration for an lcd display is shown in figure 6, page 16, followed by a quick reference table in table 4, page 18. the physical pin configuration for a led display is shown in figure 7, page 17, followed by a quick reference table in table 5, page 19. t able 1: SOC-3000 p in c onfiguration for lcd d isplay pin name description 2 nd function description pull-up resistor 1 kin4 i.o 15.3 2 kin3 i.o 15.4 3 kin2 i.o 15.5 4 kin1 i.o 15.6 5 kin0 keyboard controller input see ?keyboard controller?, page 31 i.o 15.7 i/o, see ?i/o operation?, page 65 50k 6 vdd digital power supply 7 buzzer / p1.7 (cpu) buzzer 25k 8 p1.5 (cpu) 9 p1.4 (cpu) cpu i/o port see note 11 10k 10 xtal out 11 xtal in frequency clock source 12 txd serial communication tx 13 rxd serial communication rx 100k 14 pwr_off / p3.4/timer 0 power off control p3.4 (cpu) 15 main_det / p3.5 /timer1 battery/ac power supply detector input p3.5 (cpu) 16 el / p1.6 (cpu) electro-luminescent light control see note 11 p1.6 (cpu) cpu i/o ports, or: p3.4 ? timer 0 50k 17 vlcd lcd display voltage 18 bp1 out 4.0 19 bp2 out 4.1 20 bp3 out 4.2 21 bp4 lcd display multiplexer backplanes, see ?lcd controller/driver?, page 35 out 4.3 i/o see ?i/o operation?, page 69
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 10 july, 2002 pin name description 2 nd function description pull-up resistor 22 s1 out 5.0 23 s2 out 5.1 24 s3 out 5.2 25 s4 out 6.0 26 s5 out 6.1 27 s6 out 6.2 28 s7 out 6.3 29 s8 out 7.0 30 s9 out 7.1 31 s10 out 7.2 32 s11 out 7.3 33 s12 out 8.0 34 s13 out 8.1 35 s14 out 8.2 36 s15 out 8.3 37 s16 out 9.0 38 s17 out 9.1 39 s18 out 9.2 40 s19 41 s20 42 s21 43 s22 44 s23 45 s24 46 s25 47 s26 48 s27 out 10.0 49 s28 out 11.0 50 s29 out 11.1 51 s30 out 11.2 52 s31 out 11.3 53 s32 out 12.0 54 s33 out 12.1 55 s34 out 12.2 56 s35 out 12.3 57 s36 out 12.4 58 s37 lcd display segment see ?lcd controller/driver?, page 35 out 13.0 i/o see ?i/o operation?, page 69
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 11 july, 2002 pin name description 2 nd function description pull-up resistor 59 s38 out 13.1 60 s39 out 13.2 61 s40 out 13.3 62 vcc power supply 63 reset reset 50k 64 gnd digital ground 65 vdet/ int0~ power voltage detector input / interrupt 0 input 66 sig2+ 2nd ad channel input signal + 67 sig2? 2nd ad channel input signal ? 68 agnd analog ground 69 sen? load cell sense input ? 70 sig1? load cell signal input ? 71 sig1+ load cell signal input + 72 sen+ load cell sense input + 73 avcc analog power supply 74 kout7 i.o 14.0 75 kout6 i.o 14.1 76 kout5 i.o 14.2 77 kout4 i.o 14.3 78 kout3 i.o 14.4 79 kout2 i.o 14.5 80 kout1 i.o 14.6 81 kout0 keyboard controller inputs see ?keyboard controller?, page 31 i.o 14.7 82 kin7 i.o 15.0 83 kin6 i.o 15.1 84 kin5 keyboard controller inputs see ?keyboard controller?, page 31 i.o 15.2 i/o see ?i/o operation?, page 69 50k
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 12 july, 2002 t able 2: SOC-3000 p in c onfiguration for led d isplay pin name description 2 nd function description pull-up resistor 1 kin4 i.o 15.3 2 kin3 i.o 15.4 3 kin2 i.o 15.5 4 kin1 i.o 15.6 5 kin0 keyboard controller input see ?keyboard controller?, page 31 i.o 15.7 i/o see ?i/o operation?, page 69 50k 6 vdd digital power supply 7 buzzer / p1.7 (cpu) buzzer p1.7=?1? ? on p1.7=?0? ? off see note 10, 11 25k 8 p1.5 (cpu) 9 p1.4 (cpu) cpu i/o port. see note 11 10k 10 xtal out 11 xtal in frequency clock source 12 txd serial communication tx 13 rxd serial communication rx 100k 14 pwr_off / p3.4 / timer 0 power off control p3.4 (cpu) 50k 15 main_det / p3.5 / timer 1 battery/ac power supply detector input p3.5 (cpu) cpu i/o port, or: p3.4 ? timer 0 p3.5 ? timer 1 see note 11 16 el electro-luminescent light control p1.6 (cpu) see note 11 17 nc not used 18 out 4.0 out 4.0 19 out 4.1 out 4.1 20 out 4.2 out 4.2 21 out 4.3 outputs. out 4.3 22 seg a1 out 5.0 23 seg b1 out 5.1 24 seg c1 out 5.2 25 seg d1 out 6.0 26 seg e1 out 6.1 27 seg f1 out 6.2 28 seg g1 out 6.3 29 seg dp1 out 7.0 30 seg a2 out 7.1 31 seg b2 out 7.2 32 seg c2 out 7.3 33 seg d2 display segment out, see ?led parallel display controller block diagram?, page 45 out 8.0 i/o see ?i/o operation?, page 69
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 13 july, 2002 pin name description 2 nd function description pull-up resistor 34 seg e2 out 8.1 35 seg f2 out 8.2 36 seg g2 out 8.3 37 seg dp2 out 9.0 38 seg a3 out 9.1 39 seg b3 out 9.2 output, i/o see ?i/o operation?, page 69 40 seg c3 41 seg d3 42 seg e3 43 seg f3 44 seg g3 45 seg dp3 display segment out, see ?led parallel display controller block diagram?, page 45. 46 dig 1 47 dig 2 48 dig 3 out 10.0 49 dig 4 out 11.0 50 dig 5 out 11.1 51 dig 6 out 11.2 52 dig 7 display digit mux control see ?led parallel display controller?, page 45 out 11.3 i/o see ?i/o operation?, page 69 53 out 12.0 54 out 12.1 55 out 12.2 56 out 12.3 57 out 12.4 output see ?i/o operation?, page 69 58 led_si_clk out 13.0 59 led_si_data out 13.1 60 led_si_st out 13.2 61 led_si_bl led serial interface display module clock, data, strobe and blank see ?led serial interface display controller?, page 49. out 13.3 i/o see ?i/o operation?, page 69 62 vcc power supply 63 reset reset 50k 64 gnd digital ground 65 vdet/ int0~ power voltage detector input / interrupt 0 input 66 sig2+ 2 nd adc channel input signal + 67 sig2? 2 nd adc channel input signal ? 68 agnd analog ground 69 sen? load cell sense input ?
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 14 july, 2002 pin name description 2 nd function description pull-up resistor 70 sig1? load cell signal input ? 71 sig1+ load cell signal input + 72 sen+ load cell sense input + 73 avcc analog power supply 74 kout7 i.o 14.0 75 kout6 i.o 14.1 76 kout5 i.o 14.2 77 kout4 i.o 14.3 78 kout3 i.o 14.4 79 kout2 i.o 14.5 80 kout1 i.o 14.6 81 kout0 keyboard controller output, see ?keyboard controller?, page 31 i.o 14.7 82 kin7 i.o 15.0 83 kin6 i.o 15.1 84 kin5 keyboard controller input, see ?keyboard controller?, page 31 i.o 15.2 i/o see ?i/o operation?, page 69 50k g lossary of t erms term definition bp backplane clk clock dig digit i.o input/output kin keyboard in kout keyboard out p/pwr power reg register rx receive seg segment si serial interface tx transmit
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 15 july, 2002 t able 3: n otes on SOC-3000 p in c onfiguration # component remarks 1 lcd controller/driver ? bit programmable 2 led controller ? v oh @ i o = 1.5ma ? bit programmable 3 output pins cmos?3.3v 4 input pins cmos?3.3v 5 vdet ? less than 5v ? threshold level ? 2.1v. ? the input (on the analog chip) tolerates input voltage applied while the SOC-3000 is powered off. 6 vdd 3.3v 5% 7 vcc 5v 5% 8 avcc 5v 5% 9 keyboard controller bit programmable 10 buzzer p1.7 is used as the buzzer control pin. during power-up the SOC-3000 asserts 3 pulses on this line. 11 port 1.x manipulation of this pin should be made using bit mapping of the port, since bits p1.0-p1.1 are allocated to the bank select register. soc3000 plcc84 p11 p1 p84 p75 p33 p53 p12 p32 p7 4 p5 4 pin 1 identifier f igure 5: SOC-3000 p in a rrangement
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 16 july, 2002 f igure 6: SOC-3000 lcd d isplay p in c onfiguration
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 17 july, 2002 f igure 7: SOC-3000 led d isplay p in c onfiguration
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 18 july, 2002 t able 4: SOC-3000 q uick r eference p in c onfiguration for lcd d isplay pin name 1 kin4 / i.o 15.3 2 kin3 / i.o 15.4 3 kin2 / i.o 15.5 4 kin1 / i.o 15.6 5 kin0 / i.o 15.7 6 vdd 7 buzzer / p1.7 8 p1.5 (cpu) 9 p1.4 (cpu) 10 xtal out 11 xtal in 12 txd 13 rxd 14 pwr_off / p3.4 (cpu) / timer 0 15 main_det / p3.5 (cpu) / timer 1 16 el / p1.6 (cpu) 17 vlcd 18 bp1 / out 4.0 19 bp2 / out 4.1 20 bp3 / out 4.2 21 bp4 / out 4.3 pin name 22 s1 / out 5.0 23 s2 / out 5.1 24 s3 / out 5.2 25 s4 / out 6.0 26 s5 / out 6.1 27 s6 / out 6.2 28 s7 / out 6.3 29 s8 / out 7.0 30 s9 / out 7.1 31 s10 / out 7.2 32 s11 / out 7.3 33 s12 / out 8.0 34 s13 / out 8.1 35 s14 / out 8.2 36 s15 / out 8.3 37 s16 / out 9.0 38 s17 / out 9.1 39 s18 / out 9.2 40 s19 41 s20 42 s21 pin name 43 s22 44 s23 45 s24 46 s25 47 s26 48 s27 / out 10.0 49 s28 / out 11.0 50 s29 / out 11.1 51 s30 / out 11.2 52 s31 / out 11.3 53 s32 / out 12.0 54 s33 / out 12.1 55 s34 / out 12.2 56 s35 / out 12.3 57 s36 / out 12.4 58 s37 / out 13.0 59 s38 / out 13.1 60 s39 / out 13.2 61 s40 / out 13.3 62 vcc 63 reset pin name 64 gnd 65 vdet / int 0~ 66 sig2+ 67 sig2? 68 agnd 69 sen? 70 sig1? 71 sig1+ 72 sen+ 73 avcc 74 kout7 / i.o 14.0 75 kout6 / i.o 14.1 76 kout5 / i.o 14.2 77 kout4 / i.o 14.3 78 kout3 / i.o 14.4 79 kout2 / i.o 14.5 80 kout1 / i.o 14.6 81 kout0 / i.o 14.7 82 kin7 / i.o 15.0 83 kin6 / i.o 15.1 84 kin5 / i.o 15.2
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 19 july, 2002 t able 5: SOC-3000 q uick r eference p in c onfiguration for led d isplay pin name 1 kin4 / i.o 15.3 2 kin3 / i.o 15.4 3 kin2 / i.o 15.5 4 kin1 / i.o 15.6 5 kin0 / i.o 15.7 6 vdd 7 buzzer / p1.7 8 p1.5 (cpu) 9 p1.4 (cpu) 10 xtal out 11 xtal in 12 txd 13 rxd 14 pwr_off / p3.4 / timer 0 15 main_det / p3.5 / timer 1 16 el / p1.6 17 not connected 18 out / out 4.0 19 out / out 4.1 20 out / out 4.2 21 out / out 4.3 pin name 22 seg a1 / out 5.0 23 seg b1 / out 5.1 24 seg c1 / out 5.2 25 seg d1 / out 6.0 26 seg e1 / out 6.1 27 seg f1 / out 6.2 28 seg g1 / out 6.3 29 seg dp1 / out 7.0 30 seg a2 / out 7.1 31 seg b2 / out 7.2 32 seg c2 / out 7.3 33 seg d2 / out 8.0 34 seg e2 / out 8.1 35 seg f2 / out 8.2 36 seg g2 / out 8.3 37 seg dp2 / out 9.0 38 seg a3 / out 9.1 39 seg b3 / out 9.2 40 seg c3 41 seg d3 42 seg e3 pin name 43 seg f3 44 seg g3 45 seg dp3 46 dig 1 47 dig 2 48 dig 3 / out 10.0 49 dig 4 / out 11.0 50 dig 5 / out 11.1 51 dig 6 / out 11.2 52 dig 7 / out 11.3 53 out 12.0 54 out 12.1 55 out 12.2 56 out 12.3 57 out 12.4 58 out 13.0 59 out 13.1 60 out 13.2 61 out 13.3 62 vcc 63 reset pin name 64 gnd 65 vdet / int 0 ~ 66 sig2+ 67 sig2? 68 agnd 69 sen? 70 sig1? 71 sig1+ 72 sen+ 73 avcc 74 kout7/i.o 14.0 75 kout6/i.o 14.1 76 kout5/i.o 14.2 77 kout4/i.o 14.3 78 kout3/i.o 14.4 79 kout2/i.o 14.5 80 kout1/i.o 14.6 81 kout0/i.o 14.7 82 kin7/i.o 15.0 83 kin6/i.o 15.1 84 kin5/i.o 15.2
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification . revision b page 20 july, 2002
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 21 july, 2002 cpu 80c51tbo the reference source for data given here is ?m8051tbo technical specifications?, virtual ip group, inc., version m8051ts97df01. refer to this manual for complete cpu specification. features ? 8-bit cpu ? compatible with standard 80c31 ? four 8-bit i/o ports ? three 16-bit timers ? on-chip oscillator and clock circuitry ? 256-byte on-chip, 8051-compatible sfr ram ? 64kbyte program memory with bank switching ? 4kbyte xdata ram for data memory ? high-speed architecture of 4 cycles/instruction ? dual data pointers advantages ? fast running and improved performance ? no wasted clock and memory cycles ? works efficiently with all types of peripheral devices ? improved power consumption characteristics ? on-chip power-on/reset architecture the cpu block diagram is presented in figure 8. address bus data bus program counter dptr0 pc increment buffer pc address reg. dptr1 port 2 port latch p2.0 to p2.7 port 0 ad0 to ad7 timer 2 accumulator b register alu reg. 1 alu reg. 2 psw stack pointer alu timed access timer 1 timer 0 oscillator sfr ram address 256 bytes sfr 8 ram clocks and memory control power control register interrupt reg. instruction decoder xtal1 xtal2 ale psen reset control rst port 1 port 3 port latch serial port 0 port latch interrupt logic p1.0 to p1.7 p3.0 to p3.7 f igure 8: cpu b lock d iagram
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification . revision b page 22 july, 2002 memory organization the SOC-3000 is an 8051-compatible device with an 80c310 memory chip. as with all such devices, the SOC-3000 has separate address spaces for program and data memory. they are: ? flash memory ? memory space containing non-volatile, in-circuit re-programmable code and data (such as calibration data). the code in the flash memory may be in-circuit programmed at a byte level, although it must first be erased, the erasing being performed in page blocks. the program memory space can be in-circuit programmed through the serial port. ? ram memory ? random access memory used as ?scratchpad memory? for the software. flash (program & non-volatile data) memory mapping and usage the 8051-compatible SOC-3000 supports a maximum code space of 64k. programs larger than 64k are handled by bank switching to select one of a number of code banks residing at one physical address. in the SOC-3000, there is one 32k common-program area mapped from address 0000h to 7fffh (figure 9) and three 32k code banks mapped from code address 8000h to ffffh (figure 9). the code banks are selected using bits in a memory- mapped address. the flash memory may be dynamically allocated between the program and the non-volatile data memory. this eliminates the need of external eeprom usually used for storing calibration parameters and other non-volatile variable data. the flash memory is built of 4k bytes of erasable blocks whose boundary is located at 4k address (multiples of 1000h). f800h rom bank 1 32k rom bank 2 32k rom bank 3 32k flash data memory ffffh 8000h rom common area 32k fffh 4k reserved by system 0000h 7fffh f igure 9: SOC-3000 p rogram m emory m ap
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 23 july, 2002 application program start address the start address of the application program should be located at 1000h, as the first 4kbytes are reserved for the SOC-3000/i system. serial downloading (in-circuit programming) as part of its embedded boot software the SOC-3000 facilitates serial code and data download via the standard uart serial port. serial download mode is automatically entered upon power-up or reset if one of the following conditions exist: 1. no valid program is programmed in the flash memory. 2. a request for download process was initiated via the uart during the first 200 ms after power-up/reset. once in this mode, you can download code or data files into the flash memory, while the device is located on its target board. the is the pc serial download utility, cybratech cloader executable, is provided together with the device and its documentation and software library. the SOC-3000/i may be programmed only if, within 200ms after power-up or reset, it establishes communication with the cloader executable , or if the application program is not available or not valid (checksum error). figure 10describes the startup procedure of the SOC-3000.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification . revision b page 24 july, 2002 power-up / reset is cloader communicating ? yes no 200 ms elapsed ? no start programming mode yes is the application program ok? no yes start application program f igure 10: SOC-3000/i s tartup p rocedure using the flash for data memory the flash memory may be used for storing non-volatile data. to update the data area while the program is running, the flash must be defined as data area instead of as code area. cybratech flash manager software manages this process in an efficient and reliable manner. it provides the means to read, write, erase and update the flash data area. a detailed description of the cybratech flash manager function is included in the SOC-3000 software function library user manual, document number: soc-0000-sw01-om.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 25 july, 2002 data memory mapping the SOC-3000 ?scratchpad? data memory is stored in 4kbyte ram mapped as xdata, as shown in figure 11, in addition to the cpu 256-byte ram. 8bffh 8000h 8fffh external ram 3k reserved 8c00h f igure 11: SOC-3000 d ata m emory m ap memory bank select register the memory bank select register is implemented using the 80c51tbo port 1 bits p1.0 ? p1.1. p1.0 is the least significant bit. manipulation of other port 1 i/o pins must be carried out without affecting these bits. note : the page register is write only! reading p1.0-p1.1 may result in an ambiguous result. cpu sfrs and configuration registers (cfr) the cpu sfrs (special function registers) are compatible with the 8051 instruction set. for more information, please refer to ?m8051tbo technical specifications?. the cpu controls the peripherals and their operating modes through configuration registers (cfr) mapped as xdata. the cfr registers for each peripheral are described below in table 32, page 62. instruction set all instructions in the 8051-compatible SOC-3000 instruction set perform the same functions as in the 8051. they identically oversee bit and flag operations and other status functions. only the clock configuration differs. for absolute timing of real time events, the timing of software loops can be calculated. however, counter/timers default to run at the older 12 clocks per increment. in this way, timer-based events occur at the standard intervals with software executing at higher speed. timers optionally can run at 4 clocks per increment to take advantage of faster processor operation.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification . revision b page 26 july, 2002 in the SOC-3000, the movx instruction may take only two machine cycles or eight oscillator cycles, while the ?mov direct, direct? instruction uses three machine cycles or 12 oscillator cycles. thus, the execution times of the two instructions differ. this is because the SOC-3000 usually uses one instruction cycle for each instruction byte. note that a machine cycle requires just four clocks, and provides one ale pulse per cycle. many instructions require only one cycle, but some require five. reset the reset signal is generated by an internal circuitry in the asic. the signal thresholds are: reset falling edge on vcc=3.98v. reset rising edge on vcc=4.19v. the hystheresis of the reset signal is set so that normal operation of the internal flash memory is guaranteed. interrupt vectors the interrupt vectors of the SOC-3000/i are shifted compared with the interrupt vectors of a standard 80c51tbo vectors by an offset of 1000h. table 6 details the SOC-3000/i interrupt vectors: t able 6: i nterrupt v ectors d escription interrupt source flag vector location priority external interrupt 0 ie0 1003h 1 (highest) timer 0 overflow tf0 100bh 2 external interrupt 1 ie1 1013h 3 timer 1 overflow tf1 101bh 4 serial port ri + ti 1023h 5 timer 2 overflow tf2 + exf2 102bh 6
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 27 july, 2002 adc c ontroller i nterface features ? resolution ? 20 bit ? programmable gain ?0.5, 0.75, 1, 1.5, 2 ? programmable sample rate of 5, 10 or 20 samples per second ? voltage detection input and alarm controller registers adc converter (adc) controller interface includes a semaphore register (one byte), a control register (two bytes) and a data/status register (four bytes). the adc controller registers are defined in table 7. t able 7: adc c ontroller r egisters d escription function address bit remarks controller clock enable c200h 7 1 = enable 0 =disable controller reset c406h all 0xff = reset semaphore register e100h 0-1 read/write data registers e103h to e106h all read only control register e101h to e102h all write only semaphore register the semaphore register bit definitions are shown in table 8. t able 8: adc c ontroller i nterface s emaphore r egister b it d efinitions address bit 7 ? bit 2 bit 1 bit 0 (lsb) e100h don?t care tx semaphore (controller to adc converter) rx semaphore (adc converter to controller) control register the control register bit definitions and its functions and are given in table 9, page 28.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification . revision b page 28 july, 2002 t able 9: adc c ontroller i nterface c ontrol r egister b it f unctions byte # address bit function settings 0 (lsb) interrupt enable 0 = disable 1 = enable 1 e101h 1-7 don?t care don?t care 0-1 (bit 0 ? lsb) sample rate 00 = 20 hz (default) & f.s=100,000 counts 01 = 10 hz & f.s. = 200,000 counts 10 = 10 hz& f.s. = 100,000 counts 11 = 5 hz& f.s. = 200,000 counts 2-4 gain power down 000 = 0.50 001 = 0.75 010 = 1.00 011 = 1.50 100 = 2.00 111 = power down 5 adc channel 0 = main (default) channel 1 = secondary channel 6 don?t care don?t care 2 e102h 7 don?t care don?t care status/data registers the data register bit definitions are shown in table 10. the bit functions are described in table 11. t able 10: adc c ontroller i nterface d ata r egister b it d efinitions byte # address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 1 e103h d7 d6 d5 d4 d3 d2 d1 d0 2 e104h d15 d14 d13 d12 d11 d10 d9 d8 3 e105h g1/pd1 g0/pd0 sr1 sr0 d19 d18 d17 d16 4 e106h 0 0 0 0 0 0 ch g2/pd2 t able 11: adc c ontroller i nterface d ata r egister b it f unctions bit function d i adc reading data d0 = lsb d19 = msb sr i sample rate g i /pd i gain/power down ch active adc channel
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 29 july, 2002 operation initialization: to enable the adc controller interface: 1. enable the adc controller interface clock source in clock enable register c200h: set c200h, bit 7 to 1. 2. reset the adc controller interface: write ff to register c406h. 3. set the configuration registers (cfr) address for adc controller interface function: cfr address c10ch = 1fh. 4. enable interrupt: set e101h, bit 0 to 1. 5. check the semaphore byte at address e100h. if receive semaphore bit at e100h is ready (bit 0 = 0), signaling the cpu that the adc controller can receive data, the cpu performs the following operations: a. sets the transmit semaphore bit at e100h to busy (bit 1 = 1) to prevent transmission of data from the adc controller. b. programs the control register e101?e102h of the adc controller to initialize controller operation. normal operation: 6. after the adc controller has been initialized, the following operations are performed: a. the cpu resets the transmit semaphore bit at e100h to ready (bit 1 = 0 ) to signal the adc controller that it can now transmit data. b. the adc controller sets the receive semaphore bit at e100h to busy (bit 0 = 1 ) to prevent further data transmission to the controller. c. the adc controller sends adc converter data to data registers at e103h to e106h. 7. after sending the data of registers e103h to e106h , the adc controller resets the receive semaphore bit at e100h to ready (bit 0 = 0 ), signaling the cpu that the controller can now receive new data. one adc controller operation cycle is now complete. steps 6 through 7 are repeated cyclically. the adc internal counts output is dependent upon the input signal, the gain and the operation mode setting. table 12 defines the relation between the internal counts output of the zero signal input of the full-scale signal and the adc settings.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification . revision b page 30 july, 2002 t able 12: adc o utput c ounts v s . adc s ettings gain sample rate * (hz) adc resolution mode * (in counts) adc output at zero signal input (counts) maximum full-scale input (milli-volts) adc output (counts) 20 100,000 153,200 10 205,000 10 100,000 153,200 10 205,000 10 200,000 306,400 10 412,000 0.5 5 200,000 306,400 10 412,000 20 100,000 153,200 10 231,000 10 100,000 153,200 10 231,000 10 200,000 306,400 10 464,000 0.75 5 200,000 306,400 10 464,000 20 100,000 153,200 10 257,000 10 100,000 153,200 10 257,000 10 200,000 306,400 10 514,000 1.0 5 200,000 306,400 10 514,000 20 100,000 153,200 6.6 257,000 10 100,000 153,200 6.6 257,000 10 200,000 306,400 6.6 514,000 1.5 5 200,000 306,400 6.6 514,000 20 100,000 153,200 5 257,000 10 100,000 153,200 5 257,000 10 200,000 306,400 5 514,000 2.0 5 200,000 306,400 5 514,000 * adc resolution mode is defined in table 9, register e102h, bits 0-1 ? sample rate.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 31 july, 2002 k eyboard c ontroller features ? supports up to 64 keys (88) ? programmable anti-bounce mechanism (4-18 ms) ? automatic key matrix scanning ? automatically detects excessively long or constant key depression ? when interrupt mode enabled, generates an interrupt when any key is pressed or released functional description keyboard controller matrix configuration the keyboard matrix configuration showing the 8 8 matrix is given in figure 12. the key values at each junction are in hexadecimal. 00 kout 0 kin 0 10 kout 1 20 kout 2 30 kout 3 40 kout 4 50 kout 5 60 kout 6 70 kout 7 01 kin 1 11 21 31 41 51 61 71 02 kin 2 12 22 32 42 52 62 72 03 kin 3 13 23 33 43 53 63 73 04 kin 4 14 24 34 44 54 64 74 05 kin 5 15 25 35 45 55 65 75 06 kin 6 26 36 46 56 66 76 07 kin 7 17 27 37 47 57 67 77 key values are in hexadecimal. * * 16 f igure 12: k eyboard m atrix c onfiguration
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 32 july, 2002 controller registers keyboard controller interface includes a control register (one byte) and a data/status register (two bytes). the keyboard controller registers are defined in table 13. t able 13: k eyboard c ontroller r egisters d escription function address bit remarks controller clock enable c200h 2 1= enable 0= disable controller reset c400h all 0xff = reset data registers f100h to f 101h all read only control register f100h all write only registers description control register the keyboard control register bit definitions, functions, and settings are displayed in table 14. t able 14: k eyboard c ontroller c ontrol r egister b it f unctions address bit function settings 0-2 (bit 0 -lsb) anti-bounce timeout 000 = 4 ms 001 = 6 ms 010 = 8 ms 011 = 10 ms 100 = 12 ms 101 = 14 ms 110 = 16 ms 111 = 18 ms 3 interrupt enable/disable 0 = enable 1 = disable (default) f100h 4-7 don?t care don?t care data registers keyboard data is stored in two 8-bit registers. the data register bit functions are shown in table 15.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 33 july, 2002 n ote when control register address f101h , bit 7 is set to 1 (released), key-code value bits 0 to 6 in address f101h are meaningless. t able 15: k eyboard c ontroller d ata r egister b it d efinitions byte # address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 1 f100h x x x x x x x key error 0 = legal 1 = error 2 f101h release sign 0 = pressed 1 = released d6 d5 d4 d3 d2 d1 d0 operation at power on, the keyboard controller is reset and the scanning rate is set to 10 s. initialization: to enable the keyboard controller: 1. enable the keyboard controller clock source in clock enable register c200h : set c200h, bit 2 to 1 . 2. reset the keyboard controller: write ff to register c400h . 3. set cfr address for keyboard controller function: cfr addresses c10dh and c10eh = ff (table 32, page 62). this causes the following results: ? enables keyboard input pins ( 1 to 5 and 82 to 84) (table 32; page 62; table 1, page 9; table 2, page 12) ? enables keyboard output pins ( 74 to 81 ) (table 32, table 1, table 2) 4. enable keyboard interrupt: set f100h, bit 3 to 0 . 5. set anti-bounce timeout: set f100h, bits 0, 1 and 2, as shown in table 14. normal operation: 6. read keyboard key-code value bits, as follows: ? read register f100h, bit 0: if 0 , key-code value is legal. if 1 , key-code value is illegal (error). ? read key code from register f101h, bits 0 to 6: when key pressed, values are valid. ? read f101h, bit 7: if 0, key pressed and keyboard values (bits 0 to 6) are valid. if 1, key released and keyboard values are meaningless.

cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 35 july, 2002 lcd c ontroller /d river features ? selectable backplane drive configuration, static or multiplex drive ratios of 1:2, 1:3 or 1:4 ? selectable display bias configuration, static, or 1/2 bias or 1/3 bias ? internal lcd bias generation with voltage- follower buffers ? drives up to 40 segments with the capacity to generate 20 numeric characters ? 20 8-bit memory display data ? user-selected lcd voltages functional description the SOC-3000 lcd controller/driver interfaces to lcd (liquid crystal display) with low multiplex rates. the controller/driver generates drive signals for static drive mode (no multiplexing) or multiplexed lcds with multiplex drive ratios of 1:2, 1:3 or 1:4, depending on the number of backplane outputs. the driver supports up to four backplanes, each supporting 40 segments. the lcd controller/driver block diagram is shown in figure 13. the driver supports numeric, alphanumeric and dot matrix display configurations. the number of characters of each type that can be displayed depends on the number of backplanes and the number of segments required per character. the maximum display capacity for each display configuration is shown in table 16. lcd voltage selector display segment outputs lcd bi as generat or ? + ? + r r r v dd v lcd display latch shift register bp0 bp1 bp2 bp3 0 to 39 backplane out puts f igure 13: lcd c ontroller /d river b lock d iagram
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 36 july, 2002 t able 16: m aximum d isplay c apacity per d isplay c onfiguration number of backplanes segments or symbols numeric (7 segments) 4 160 20 3 120 15 2 80 10 1 40 5 lcd bias generator the operative lcd voltage is derived from v dd ? v lcd (figure 13). the three resistors connected in series between v dd and v lcd in the bias generator function as a voltage divider to produce 1/2 (for the 1:2 multiplex drive ratio) and 1/3 (for the 1:2, 1:3 and 1:4 multiplex drive ratio) biasing voltages. the bias configuration for each of the multiplex drive ratios is given in table 17. for additional information on lcd drivers refer to lcd driver components datasheets such as phillips pcf8756. t able 17: lcd b ias c onfigurations multiplex drive mode # backplanes # levels bias configuration static 1 2 static 1:2 2 3 1/2 1:2 2 4 1/3 1:3 3 4 1/3 1:4 4 4 1/3 drive mode waveforms the waveforms for the static drive mode are given in figure 14, page 37. the waveforms for the 1:2 multiplex drive ratio?1/2 bias are given in figure 15, page 38. the waveforms for the 1:2 multiplex drive ratio?1/3 bias are given in figure 16, page 39. the waveforms for the 1:3 multiplex drive ratio are given in figure 17, page 40. the waveforms for the 1:4 multiplex drive ratio are given in figure 18, page 41.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 37 july, 2002 driver waveforms lcd segment waveforms on/off backplane 0 segment n on segment n+1 off v dd v lcd v dd v lcd v dd v lcd segment on + v oper 0v ? v oper + v oper 0v ? v oper segment off t frame f igure 14: s tatic d rive m ode w aveforms
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 38 july, 2002 driver waveforms backplane 0 segment n segment n+1 backplane 1 segment on segment off lcd segment waveforms on/off f igure 15: 1:2 m ultiplex d rive r atio ?1/2 b ias w aveforms
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 39 july, 2002 driver waveforms backplane 0 segment n segment n+1 backplane 1 segment on segment off lcd segment waveforms on/off t frame f igure 16: 1:2 m ultiplex d rive r atio ?1/3 b ias w aveforms
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 40 july, 2002 driver waveforms backplane 0 t frame backplane 1 backplane 2 segment n segment n+1 segment n+2 segment on segment off lcd segment waveforms on/off f igure 17: 1:3 m ultiplex d rive r atio w aveforms
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 41 july, 2002 driver waveforms backplane 0 t frame backplane 1 backplane 1 segment n segment n+1 backplane 2 backplane 3 segment n+2 segment n+3 segment on segment off lcd segment waveforms on/off f igure 18: 1:4 m ultiplex d rive r atio w aveforms
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 42 july, 2002 registers description lcd controller /driver command and data are stored in a 21-byte 8-bit, static display ram with one control register and 20 data registers. the controller registers are defined in table 18. t able 18: lcd c ontroller /d river r egisters d escription function address bit remarks controller clock enable c200h 0 1= enable 0= disable controller reset c401h all 0xff = reset data registers c801h to c814h all write only control register c800h all read/write control register the control-register bit definitions and functions are displayed in table 19. the type definitions are static and dynamic : static bits update only after an external reset and first chip select (first command write cycle). dynamic bits can be updated at any time. t able 19: lcd c ontroller c ontrol r egister b it f unctions address bit name update function settings 0-1 ( 0- lsb) m0 and m1 after reset only bits 0 (m0) and 1 (m1) set the multiplex drive ratio. 00 = static (5 seven-segment digits) 01 = 1:2 (10 seven-segment digits) 10 = 1:3 (15 seven-segment digits) 11 = 1:4 (20 seven-segment digits) 2 b after reset only sets the bias voltage. 0 = 1/2 1 = 1/3 3 e anytime sets lcd display operation. 0 = disable 1 = enable 4-6 x0 (lsb), x1 and x2 after reset only bits 4 (x0), 5 (x1) and 6 (x2) set the refresh clock frequency. 000 = 52 hz 001 = 104 hz 010 = 156 hz 011 = 208 hz 100 = 62 hz 101 = 125 hz 110 = 178 hz 111 = 250 hz c800h 7 c anytime sets the command operating mode. 0 = continuous data reading 1 = command only
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 43 july, 2002 data registers lcd display data is stored in a 20-byte 8-bit ram. the number of registers used depends on the number of digits displayed, 5, 10, 15 or 20. the data register bit definitions for a 20-digit display, for which the entire ram is used, are shown in table 20. t able 20: lcd c ontroller d ata r egister b it d efinitions ? 20-d igit d isplay byte # address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 c801h dp g f e d c b a 2 c802h dp g f e d c b a ? ? ? ? ? ? ? ? ? ? 20 c814h dp g f e d c b a for other displays, data registers utilization is as follows: ? for 15-digit command, write data to c801h to c80fh ? for 10-digit command, write data to c801h to c80ah ? for 5-digit command, write data to c801h to c805h each byte in the register defines a seven-segment digit and decimal point (dp). each bit of a register address corresponds to a segment of each digit, as shown in figure 19. when the bit is set to 1 , it is on. when it is set to 0 , it is off. figure 19 also shows the backplane outputs per lcd digit for each multiplex drive ratio. a d dp static bp 0 g c e f b dp 1:2 multiplex a d bp 0 g c e f b bp 1 dp d 1:3 multiplex bp 0 a g c e f b bp 1 bp 2 dp 1:4 multiplex bp 0 bp 1 bp 3 bp 2 a d g c e f b f igure 19: b ackplane o utputs per lcd d igit
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 44 july, 2002 operation initialization: at power on, the lcd controller performs the following operations: 1. resets its backplane and segment outputs to v dd . after power on, the actual operating lcd voltage v oper is set according to the multiplexing drive mode and the bias generator. 2. after reset, the lcd pins are routed to the output function. to enable the lcd controller: 1. enable the lcd controller clock source in clock enable register c200h : set c200h, bit 0 to 1 . 2. reset the lcd controller: write ff to register c401h . 3. set cfr addresses for lcd controller function: cfr addresses c101h to c10bh = 00h (table 32, page 62). this enables lcd controller output pins ( 18 to 61 ) (table 32, page 62; table 1, page 9). normal operation: 4. write data to lcd data registers c801h to c814h . 5. set write command in lcd control register c800h . 6. repeat steps 4 and 5 for new data. the trigger for sending the data out to the display interface is: programming the control register at address c800h and writing data to the lcd data registers (c801h to c814h).
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 45 july, 2002 led p arallel d isplay c ontroller features ? supports up to 21 digits (7 segments + decimal point) ? power-save by led refresh mechanism ? programmable-display data registers ? supports common-anode, seven-segment led functional description the led display block diagram showing the relationship between the 21-digit led display, the SOC-3000 led controller and the data register is given in figure 20. the led controller timing diagram is shown in figure 21. soc?3000 seg a?2 seg b?2 seg c?2 seg d?2 seg e?2 seg f?2 seg g?2 dp?2 seg a?3 seg b?3 seg c?3 seg d?3 seg e?3 seg f?3 seg g?3 dp?3 seg a?1 seg b?1 seg c?1 seg d?1 seg e?1 seg f?1 seg g?1 dp?1 dig 1 dig 2 dig 3 dig 4 dig 5 dig 6 dig 7 a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp d101 d102 d103 d104 d105 d106 d107 dig 1 dig 2 dig 3 dig 4 dig 5 dig 6 dig 7 seg a?1 seg b?1 seg c?1 seg d?1 seg e?1 seg f?1 seg g?1 dp?1 reg. address a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp d108 d109 d10a d10b d10c d10d d10e dig 1 dig 2 dig 3 dig 4 dig 5 dig 6 dig 7 seg a?2 seg b?2 seg c?2 seg d?2 seg e?2 seg f?2 seg g?2 dp?2 reg. address a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp d10f d110 d111 d112 d113 d114 d115 dig 1 dig 2 dig 3 dig 4 dig 5 dig 6 dig 7 seg a?3 seg b?3 seg c?3 seg d?3 seg e?3 seg f?3 seg g?3 dp?3 reg. address f igure 20: led p arallel d isplay c ontroller b lock d iagram
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 46 july, 2002 500 s segment dig 1 dig 2 440 s 440 s 500 s 30 s 30 s 60 s f igure 21: led p arallel d isplay c ontroller t iming d iagram registers description the led controller registers are defined in table 21. t able 21: led p arallel d isplay c ontroller d river r egisters d escription function address bit remark controller clock enable c200h 1 1= enable 0= disable controller reset c402h all 0xff = reset semaphore bit d100h 0 read only data registers d101h to d115h all write only led display data is stored in a 21-byte 8-bit static display ram. the display ram has one read-only semaphore register containing the semaphore byte and 21 write-only data registers. all 22 bytes (one semaphore byte and 21 data bytes) must be written before any new data is applied.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 47 july, 2002 semaphore register the semaphore register bit definitions are shown in table 22. t able 22: led p arallel d isplay c ontroller s emaphore r egister b it d efinitions address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) d100h x x x x x x x e only bit 0, the semaphore bit, is active in the led controller control register (table 23). the semaphore is used to synchronize the access to the control registers. t able 23: led p arallel d isplay c ontroller s emaphore r egister b it f unctions bit name type function settings 0 e read-only semaphore bit 0 = ready 1 = busy data registers led data is stored in a 21-byte 8-bit ram. the data is organized in three groups of seven digits, as follows: ? group 1: d101h to d107h - multiplexed on sec a1 to dp1 pins. ? group 2: d108h to d10eh - multiplexed on sec a2 to dp2 pins. ? group 3: d10fh to d115h - multiplexed on sec a3 to dp3 pins. the data register bit definitions for a 21-digit display are shown in table 24. t able 24: led p arallel c ontroller d ata r egister b it d efinitions group byte # address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 1 d101h dp g f e d c b a 2 d102h dp g f e d c b a 1 3 to 7 d103h to d107h dp g f e d c b a 8 d108h dp g f e d c b a 9 d109h dp g f e d c b a 2 10 to 14 d10ah to d10eh dp g f e d c b a 15 d10fh dp g f e d c b a 16 d110h dp g f e d c b a 3 17 to 21 d111h to d115h dp g f e d c b a note: the trigger for sending the data to the display hardware is writing data to address d115h.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 48 july, 2002 operation at power-on or reset the led parallel display controller is disabled. initialization: to enable the led parallel display controller: 1. enable the controller clock source in clock enable register c200h : set c200h, bit 1 to 1 . 2. reset the controller: write ff to register c402h . 3. set cfr addresses for led parallel display controller function: cfr addresses c103h to c109h = 55h , cfr address c10a = 15h (table 32, page 62). these result in the following operations: ? enable led parallel display controller output pins ( 22 to 52 ) (table 32, page 62; table 2, page 12). ? check semaphore bit in led parallel display controller semaphore register at address d100h . normal operation: 4. if semaphore bit is ready (bit 0 set to 0 ), write data to data register addresses d101h to d115h . 5. set write command: write 01h to d100h . the trigger for sending the data out to the display serial interface is: ? programming the semaphore register at address d100h and writing data to the 21 data registers (d101h to d115h). or ? programming the semaphore register at d100h and writing data to the last data register at d115h. as soon as the controller starts to send the data, it sets the semaphore bit to 1 , indicating that it is busy. when the controller finishes data output, it resets the semaphore bit to 0 , indicating that it is available for a new operation.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 49 july, 2002 led s erial i nterface d isplay c ontroller features ? supports up to 24 digits ? serial interface ? programmable control-signal polarity ? programmable data registers ? supports common-anode, seven-segment led functional description the led serial interface display comprises three groups of eight digits. the controller diagram showing the division of the 24-byte register into three eight-byte groups and the operation cycle is given in figure 22. the led serial interface display controller timing diagram is shown in figure 23. the clock rate is 2 mhz. a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp digit 6 digit 5 digit 4 digit 3 digit 2 digit 1 seg a seg b seg c seg d seg e seg f seg g dp a g d c e f b dp di gi t 8 a g d c e f b dp di gi t 7 group 1 a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp digit 6 digit 5 digit 4 digit 3 digit 2 digit 1 seg a seg b seg c seg d seg e seg f seg g dp a g d c e f b dp di gi t 8 a g d c e f b dp di gi t 7 group 2 a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp a g d c e f b dp digit 6 digit 5 digit 4 digit 3 digit 2 digit 1 seg a seg b seg c seg d seg e seg f seg g dp a g d c e f b dp di gi t 8 a g d c e f b dp di gi t 7 group 3 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x group 3 group 2 group 1 digit 1 cycle 1 cycle 8 the controller transmits cycles 1 to 8 continuously. f igure 22: led s erial i nterface d isplay b lock d iagram
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 50 july, 2002 blank blank / 20 s strobe strobe / 20 s 20 s t = 400 s clock clock / t1 = 8 s data f igure 23: led s erial i nterface c ontroller t iming d iagram registers description the led serial controller registers description is given in table 25. t able 25: led s erial c ontroller d river r egisters d escription function address bit remarks controller clock enable c200h 5 1= enable 0= disable controller reset c403h all 0xff = reset semaphore register d201h read only data registers group 1 group 2 group 3 d201h to d208h d209h to d210h d211h to d218h write only write only write only control register d200h read/write led data is stored in a 24-byte 8-bit static display ram. the data registers are divided into three groups, each group containing eight bytes with the segment data for eight digits. thus, the led display can be formatted to display eight, 16 or 24 digits. the display ram has one read/write control register containing the command byte and a read-only semaphore byte that informs the system if the display is busy or ready to initiate writing of led data. the semaphore byte address also serves as first address of the write-only data register. the trigger for sending the data out to the display serial interface is programming the control register at address d200h. as soon as the controller starts to send data, it sets the semaphore byte to ffh , indicating that it is busy. the data is sent serially, group 1 digit 8 (left-most digit of the first group) most- significant bit (msb) first, and continuously until group 3 digit 1 least-significant bit (lsb) last.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 51 july, 2002 when the controller has finished data output, it resets the semaphore byte to 0 , indicating that it is available for a new operation. control register the definitions and functions of the control-register command-byte bits are displayed in table 26. t able 26: led s erial i nterface d isplay c ontrol r egister b it f unctions address bit name function settings 0 (lsb) c command bit 0 = command only 1 = command + data 1 x n/a don?t care 2 blank polarity sets the blank polarity. 0 = negative logic 1 = positive logic 3 strobe polarity sets the strobe polarity. 0 = negative logic 1 = positive logic 4 clock polarity sets the clock polarity. 0 = negative logic 1 = positive logic 5 e enables and disables the display. 0 = disable display 1 = enable display 6 block opens communication or blocks the hardware communication lines. 0 = close communication 1 = open communication d200h 7 n/a n/a don?t care semaphore register the semaphore byte is located at address d201h , which is the first address of the write-only data register. this address is read-only for the semaphore byte. the semaphore byte bit definitions are identical. the settings are: ? controller is busy : bits 0 to 7 set to 1 (ffh) . ? controller is ready : bits 0 to 7 set to 0 (00h) .
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 52 july, 2002 data registers the display data is stored in a 24-byte 8-bit ram area. the data register bit definitions for a 21-digit display are shown in table 27. the registers are write-only. t able 27: led s erial i nterface d isplay d ata r egister b it d efinitions group # digit # byte # address bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 8 1 d201h dp g f e d c b a 7 2 d202h dp g f e d c b a 6 3 d203h dp g f e d c b a 5 4 d204h dp g f e d c b a 4 5 d205h dp g f e d c b a 3 6 d206h dp g f e d c b a 2 7 d207h dp g f e d c b a 1 1 8 d208h dp g f e d c b a 8 9 d209h dp g f e d c b a 7 10 d20ah dp g f e d c b a 6 11 d20bh dp g f e d c b a 5 12 d20ch dp g f e d c b a 4 13 d20dh dp g f e d c b a 3 14 d20eh dp g f e d c b a 2 15 d20fh dp g f e d c b a 2 1 16 d210h dp g f e d c b a 8 17 d211h dp g f e d c b a 8 18 d212h dp g f e d c b a 8 19 d213h dp g f e d c b a 8 20 d214h dp g f e d c b a 8 21 d215h dp g f e d c b a 8 22 d216h dp g f e d c b a 8 23 d217h dp g f e d c b a 3 8 24 d218h dp g f e d c b a
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 53 july, 2002 operation at power-on or reset the led serial interface display controller is disabled. initialization: to enable the led serial interface display controller: 1. enable the controller clock source in clock enable register c200h : set c200h, bit 5 to 1 . 2. reset the controller: write ff to register c403h . 3. check cfr address for led serial interface display controller function: cfr address c101h = aa (table 32, page 62). this results in the following operations: ? enables serial controller output pins ( 58 to 61) (table 32, page 62) ? check semaphore byte at address d201h . normal operation: 4. if semaphore byte is ready (bits 0 to 7 set to 0 ), write data to data register addresses d201h to d218h . 5. set write command at the controller control register address d200h. 6. repeat steps 4 and 5 for new data.

cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 55 july, 2002 p rogrammable f requency c ontroller features ? programmable cpu clock frequency: 16, 8, 4, 2, 1 or 0.5 mhz ? driven by a 16-mhz resonator or crystal oscillator functions ? generates independent clocks for the cpu and controllers (adc converter, display, keyboard, watchdog timer, etc.) clock generator block diagram the clock generator block diagram is presented in figure 24. functional description dividing the 16-mhz frequency source according to the control register setting generates the cpu clock frequency. the cpu clock can be set to 16, 8, 4, 2, 1 or 0.5 mhz. switching cpu frequency: ? to switch from the 16-mhz frequency to any other frequency, program the frequency- controller control register as shown in table 28. ? to switch from any frequency (other than 16 mhz) to another frequency, first switch to 16 mhz and then switch to the desired frequency. 16 mhz clock 16 mhz (default) 1/2 8 mhz 1/2 4 mhz 1/2 2 mhz 1/2 1 mhz 1/2 0.5 mhz f igure 24: c lock g enerator b lock d iagram
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 56 july, 2002 operation at power on or reset, the cpu frequency clock output is set to 16 mhz. the clocks for the controllers is fixed and derived directly from the external frequency source. the frequency controller setting derives the cpu clock, as defined in table 28. control registers description the clock frequency is programmed from a single 8-bit control register. the address of the clock frequency control register is e800h . the bit settings at e800h that define the clock frequency are given in table 28. t able 28: c lock f requency c ontrol r egister b it s ettings address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) cpu clock 0 0 0 16 mhz 0 0 1 8 mhz 0 1 0 4 mhz 0 1 1 2 mhz 1 0 0 1 mhz e800h don?t care 1 0 1 0.5 mhz
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 57 july, 2002 w atchdog t imer functions the purpose of the watchdog timer is to generate a cpu reset at specified intervals. if the SOC-3000 software does not interrupt the watchdog cycle and instead enters an erroneous state, the watchdog time carries out its cpu reset one second after the software was supposed to make its interrupt. the erroneous state may be due to a programming error. the watchdog may be disabled or re- triggered via its control register. functional description the operating parameters of the watchdog timer are presented in table 29. t able 29: w atchdog t imer o perating p arameters parameter value time constant 1 second trigger by the control register (wdi) enable/disable by the control register (enwd) power up mode disabled operation the application software controls the watchdog operation. it is automatically disabled in the in-circuit emulator (ice) mode and after power-up or reset. the application software should activate the watchdog as soon as it starts normal operation after power-on or reset conditions. the watchdog timer should be periodically re-triggered during normal operation, before the timer expires. expiration of the watchdog timer resets the cpu. if required, disabling the watchdog timer clock input can disable the watchdog. table 30 describes the operation of the watchdog timer. t able 30: w atchdog t imer c ommand s equence # command address bit setting 1 enable watchdog c200h 3 1= enable 0= disable 2 re-trigger timer f800h all ffh 3 disable watchdog c200h 3 0 control registers description setting the clock enable register (c200h), bit 3 to 1 enables the watchdog timer. setting the clock enable register (c200h), bit 3 to 0 disables the watchdog timer. writing ffh to address f800h re-triggers the watchdog.

cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 59 july, 2002 l ow v oltage d etector the low voltage detector is a supervisory circuit in which the power fail input (v det ) is compared to an internal 2.23 v reference (figure 25). the comparator output goes low when the voltage at v det is less than or equal to 2.23 v and bit 1 of register e400h equals 0 . v det is usually driven by an external voltage divider, which senses the unregulated dc input to the system 5v regulator. the voltage divider ratio can be chosen such that the voltage at v det falls below 2.23 v several milliseconds before the +5v supply falls below 4.75v. int0 is normally used to interrupt the microprocessor so that data can be stored in non-volatile memory before v cc falls below 4.75 v and the reset output goes low. the power fail comparator output returns to high when vdet>2.27v. dc unreg. SOC-3000 power fail comparator + ? v in v cc reg v det r 1 r 2 int? int? goes low if vdet < 2.23v. recommended values for resistors 1% 133k 1% 100k int? 5.19v (typ.) int? 5.3v (typ.) f igure 25: l ow v oltage d etector interrupt register the address of the power-supply interrupt register is e400h (read/write). the bit settings at e400h that define the power failure interrupt and flag are given in table 31. t able 31: p ower -f ailure i nterrupt r egister b it s ettings address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 power fail flag bit 0 (lsb) interrupt enable e400h don?t care 0 = if v det < v ref 1 = normal 0 = enabled 1 = disabled
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 60 july, 2002
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 61 july, 2002 c onfiguration r egisters (cfr) programming the configuration registers (cfr) in the cpu sets the SOC-3000 pin functions. the cfr registers include control and configuration registers that provide the interface between the cpu and the other on-chip peripherals, such as the keyboard, led and lcd controllers and input/output ports. each peripheral operates as designated in the cfr registers, where each register may be programmed to perform alternative functions. (see ?examples of pin configuration programming?, on page 85). the complete cfr-register bit assignment for all peripherals and input/output and corresponding plcc-84 pins are given on the following pages in table 32.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 62 july, 2002 t able 32: cfr b it a ssignment plcc-84 pin reg add. bit bit settings per function notes 61 7-6 00=lcd display s40 10=led-si-blank 11=out 13.3 si = serial interface 60 5-4 00=lcd display s39 10=led-si- strobe 11=out 13.2 59 3-2 00=lcd display s38 10=led-si- strobe 11=out 13.1 58 c101h 1-0 00=lcd display s37 10=led-si- clk 11=out 13.0 clk = clock 57 7 0=lcd display s36 1=out 12.4 56 6 0=lcd display s35 1=out 12.3 55 5-4 00=lcd display s34 10=out 12.2 54 3-2 00=lcd display s33 10=out 12.1 53 c102h 1-0 00=lcd display s32 10=out 12.0 52 7-6 00=lcd display s31 01=led display dig 7 10=out 11.3 dig = digit 51 5-4 00=lcd display s30 01=led display dig 6 10=out 11.2 50 3-2 00=lcd display s29 01=led display dig 5 10=out 11.1 49 c103h 1-0 00=lcd display s28 01=led display dig 4 10=out 11.0 48 7-6 00=lcd display s27 01=led display dig 3 10=out 10.0 47 5-4 00=lcd display s26 01=led display dig 2 46 3-2 00=lcd display s25 01=led display dig 1 seg = segment 45 c104h 1-0 00=lcd display s24 01=led display seg dp3 dp = decimal point 44 7-6 00=lcd display s23 01=led display seg g3 43 5-4 00=lcd display s22 01=led display seg f3 42 3-2 00=lcd display s21 01=led display seg e3 41 c105h 1-0 00=lcd display s20 01=led display seg d3 40 7-6 00=lcd display s19 01=led display seg c3 39 c106h 5-4 00=lcd display s18 01=led display seg b3 10=out 9.2
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 63 july, 2002 plcc-84 pin reg add. bit bit settings per function notes 38 3-2 00=lcd display s17 01=led display seg a3 10=out 9.1 37 1-0 00=lcd display s16 01=led display seg dp2 10=out 9.0 36 7-6 00=lcd display s15 01=led display seg g2 11=out 8.3 35 5-4 00=lcd display s14 01=led display seg f2 11=out 8.2 34 3-2 00=lcd display s13 01=led display seg e2 10=out 8.1 33 c107h 1-0 00=lcd display s12 01=led display seg d2 11=out 8.0 32 7-6 00=lcd display s11 01=led display seg c2 11=out 7.3 31 5-4 00=lcd display s10 01=led display seg b2 11=out 7.2 30 3-2 00=lcd display s9 01=led display seg a2 11=out 7.1 29 c108h 1-0 00=lcd display s8 01=led display seg dp1 11=out 7.0 28 7-6 00=lcd display s7 01=led display seg g1 11=out 6.3 27 5-4 00=lcd display s6 01=led display seg f1 10=out 6.2 26 3-2 00=lcd display s5 01=led display seg e1 10=out 6.1 25 c109h 1-0 00=lcd display s4 01=led display seg d1 10=out 6.0 24 5-4 00=lcd display s3 01=led display seg c1 10=out 5.2 23 3-2 00=lcd display s2 01=led display seg b1 10=out 5.1 22 c10ah 1-0 00=lcd display s1 01=led display seg a1 10=out 5.0
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 64 july, 2002 plcc-84 pin reg add. bit bit settings per function notes 21 6-5 00=bp4 10=out 4.3 bp = backplane 20 4-3 00=bp3 01=vpp 10=out 4.2 19 2 0=bp2 1=out 4.1 18 c10bh 1-0 00=bp1 10=out 4.0 - c10ch 7-0 ffh must be always 0xff 5 7 0=i.o 15.7 1=kin0 kin = keyboard in 4 6 0=i.o 15.6 1=kin1 i.o = input/output 3 5 0=i.o 15.5 1=kin2 2 4 0=i.o 15.4 1=kin3 1 3 0=i.o 15.3 1=kin4 84 2 0=i.o 15.2 1=kin5 83 1 0=i.o 15.1 1=kin6 82 c10dh 0 0=i.o 15.0 1=kin7 81 7 0=i.o 14.7 1=kout0 kout = keyboard out 80 6 0=i.o 14.6 1=kout1 79 5 0=i.o 14.5 1=kout2 78 4 0=i.o 14.4 1=kout3 77 3 0=i.o 14.3 1=kout4 76 2 0=i.o 14.2 1=kout5 75 1 0=i.o 14.1 1=kout6 74 c10eh 0 0=i.o 14.0 1=kout7
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 65 july, 2002 s pecial f unction r egisters (sfr) the SOC-3000/i includes special function registers (sfr) that enable the device hardware controllers and reset them. each controller description details its specific sfr operation. this section details all the sfr registers and functions. all these registers are mapped as xdata memory area. global configuration register register 0c100h is used as a general enable/disable of pin allocation to all the hardware controllers in the SOC-3000/i. upon power-up or reset this register is cleared, disabling all the hardware controllers. writing 0xff to the register activates the allocation of pins to hardware controller, as defined by programming the cfr registers. t able 33: g lobal cfr r egister address function remarks c100h enable / disable pin allocation 0x00 ? enable 0xff - disable operation 1. upon power-up or reset, the global cfr register is set, disabling all pin allocation to the hardware controllers. 2. initialize the cfr registers according to the required hardware configuration as described in section ?
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 66 july, 2002 configuration registers (cfr)? page 61. 3. initialize the hardware controllers. 4. enable the global cfr register: write 0x00 to address c100h. controllers clock enable register register c200h controls the clock source to the hardware controllers in the SOC-3000/i. each controller operation may be disabled by inhibiting its clock. t able 34: c lock e nable r egister address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) c200h adc 0 sled 0 wdt kbd pled lcd
c y b r a t ech ( 2000) l t d. s o c - 3000 / i scale - o n - c hip ? a s ic t echnical speci f ica t ion re v i sion b pa g e 67 jul y , 2002 t a b l e 35: c o n tr o llers c lock e n a ble r egister b it f unctions bit name t y pe func t ion se tt i n g s 0 (lsb) l c d re ad - w r it e enable l c d display controller clock 0 = d isable 1 = enable 1 pled read-write enable parallel led display controller clock 0 = d isable 1 = enable 2 kbd read-write enable ke y board controller clock 0 = d isable 1 = enable 3 w d t read-write enable w atch-dog timer clock 0 = d isable 1 = enable 4 - read-write n one. set al w a y s to 0. al w a y s 0. 5 sled read-write enables serial led display controller 0 = d i sable 1 = enable 6 - read-write n one. set al w a y s to 0. al w a y s 0. 7 a d read-write enables a d c controller clock 0 = d isable 1 = enable controllers reset registers the sfrs listed in table 36 provides the mechanism to reset the hardware controllers of the SOC-3000/i. t able 36: c ontrollers reset r egister address type function settings c400h write only keyboard controller reset 0xff = reset c401h write only lcd display controller reset 0xff = reset c402h write only parallel led display controller reset 0xff = reset c403h write only serial led display controller reset 0xff = reset c406h write only adc controller reset 0xff = reset
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 68 july, 2002
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 69 july, 2002 i/o o peration i/o operation is determined by the configuration registers (cfr) programming. the i/o ports are composed of two groups: ? byte-oriented output ports ? data written to the port is byte oriented (writing ffh to the port will set it to high, and writing 00h to the port will set it to low). ? bit-oriented input/output (i/o) ports ? data written to the port is byte oriented (ffh?to set the port, 00h?to reset the port). data read from the port is bit-oriented (only the port allocated bit is set/reset). table 44, the i/o ports groups, addresses and corresponding plcc-84 pins are described in table 37 and table 38. t able 37: b it -o riented i/o p orts a ddresses , p in and b it a ssignment plcc-84 pin i/o port name port address bit assignment (lsb) 5 i.o 15.7 f22a 0 0 0 0 0 0 0 x 4 i.o 15.6 f22b 0 0 0 0 0 0 x 0 3 i.o 15.5 f22c 0 0 0 0 0 x 0 0 2 i.o 15.4 f22d 0 0 0 0 x 0 0 0 1 i.o 15.3 f22e 0 0 0 x 0 0 0 0 84 i.o 15.2 f22f 0 0 x 0 0 0 0 0 83 i.o 15.1 f230 0 x 0 0 0 0 0 0 82 i.o 15.0 f231 x 0 0 0 0 0 0 0 81 i.o 14.7 f232 0 0 0 0 0 0 0 x 80 i.o 14.6 f233 0 0 0 0 0 0 x 0 79 i.o 14.5 f234 0 0 0 0 0 x 0 0 78 i.o 14.4 f235 0 0 0 0 x 0 0 0 77 i.o 14.3 f236 0 0 0 x 0 0 0 0 76 i.o 14.2 f237 0 0 x 0 0 0 0 0 75 i.o 14.1 f238 0 x 0 0 0 0 0 0 74 i.o 14.0 f239 x 0 0 0 0 0 0 0 t able 38: b yte -o riented o utput p orts a ddresses and p in a ssignment plcc-84 pin i/o function port address 61 out 13.3 f205 60 out 13.2 f206 59 out 13.1 f207
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 70 july, 2002 plcc-84 pin i/o function port address 58 out 13.0 f208 57 out 12.4 f209 56 out 12.3 f20a 55 out 12.2 f20b 54 out 12.1 f20c 53 out 12.0 f20d 52 out 11.3 f20e 51 out 11.2 f20f 50 out 11.1 f210 49 out 11.0 f211 48 out 10.0 f212 39 out 9.2 f213 38 out 9.1 f214 37 out 9.0 f215 36 out 8.3 f216 35 out 8.2 f217 34 out 8.1 f218 33 out 8.0 f219 32 out 7.3 f21a 31 out 7.2 f21b 30 out 7.1 f21c 29 out 7.0 f21d 28 out 6.3 f21e 27 out 6.2 f21f 26 out 6.1 f220 25 out 6.0 f221 24 out 5.2 f222 23 out 5.1 f223 22 out 5.0 f224 21 out 4.3 f225 20 out 4.2 f226 19 out 4.1 f227 18 out 4.0 f228
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 71 july, 2002 8051-c ompatible o n -c hip p eripherals this section describes the standard 8051 peripheral devices available to the user. these functions are fully compatible with the standard 8051 cpus and are controlled via the standard 8051 special function registers (sfrs). parallel i/o ports some of the parallel i/o ports of the 80c51tbo core are available on the SOC-3000 pins. most of the ports are already allocated to specific functions. however, the application design may require allocating different functions to these pins. table 39 list the available pins, 80c51 i/o port, default function and special precaution needed when changing the function of the pin. t able 39: a vailable p ins on the 80c51 i/o p ort pin # 80c51 port default function special precautions 7 p1.7 buzzer after power-up the SOC-3000 asserts 3 pulses on this pin 8 p1.5 none 9 p1.4 none 14 p3.4 / timer 0 none used in cybratech application for power-off control in low-power applications 15 p3.5 / timer 1 none used in cybratech application for detecting power source (ac/battery) 16 p1.6 none used in cybratech application to control lcd electro-luminescent backlight operation the i/o ports are controlled and accessible using the 80c51tbo special function registers as described in its device specification. timers/counters the 80c51 timers/counters external inputs are available for use on SOC-3000 pin #14 (timer 0) and pin #15 (timer 1). using the timers is via the 80c51 special function registers (sfrs) as described in the 80c51tbo specification.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 72 july, 2002
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 73 july, 2002 SOC-3000 i nitialization at power-up or after reset the SOC-3000 performs the following procedures: ? disabling all the peripheral controllers of the asic. ? setting the cfr and control registers to their default values. ? start the boot program (rom mask in the chip) that checks if the chip is programmed or not. if the chip is programmed it starts running the program starting at address 1000h . otherwise, it toggles the buzzer signal (pin 7) high/low three times to signal that the chip is erased and waits for software download via the serial communication port. to initialize the SOC-3000: 1. program the SOC-3000 pin configuration in the cfr registers. ? for general pin configuration for an lcd display, refer to table 1, page 9. for a quick reference, refer to table 4, page 18. ? for general pin configuration for a led display, refer to table 2, page 12. for a quick reference, refer to table 5, page 19. ? for cfr bit assignment, refer to table 32, page 62. for examples of cfr bit assignment, refer to ?example of pin configuration programming?, on page 85. 2. initialize the peripheral controllers used by the application. 3. write 0x00 to the global cfr register at address c100h . this activates all cfr registers and completes SOC-3000 initialization.

cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 75 july, 2002 SOC-3000 h ardware d esign c onsiderations and p eripheral i nterface c onnections load cell interface the SOC-3000 supports a wide range of load-cell connection configurations, each based on various combinations of the following connection options: ? 4-wire or 6-wire interface ? up to eight load cells connected in parallel ? load cell impedance range of 350 to 1000 ohms individually and in combination, these connection options enable the SOC-3000 to function on a wide range of application platforms, each having different power consumption and system configuration requirements, while using the same electronic hardware. 4-wire and 6-wire interfaces the SOC-3000 interface to the load cell carries the following electrical signals: ? sig + (signal input +) ? sig ? (signal input ?) ? sen + (excitation voltage / sense input +) ? sen ? (excitation voltage / sense input ?) a typical 4-wire load-cell connection, in which the distance between the load cells and the SOC-3000 chip is small, as in a standard retail scale, is shown in figure 26. however, in platforms requiring long wires between the load cell and the electronic hardware, such as weighing bridges, the voltage drop over the cables is significant and affects accuracy. the 6-wire interface eliminates this error factor by using the sense wires, as shown in figure 27. the sense wires serve as a reference for the adc converter, thus eliminating the voltage drop over the long excitation-voltage wires.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 76 july, 2002 regulated 5 v load cell cable (4-wires) unregulated power reg. SOC-3000 73 avcc agnd 68 69 sen- 70 sig - 71 sig + 72 sen + f igure 26: 4-w ire l oad -c ell c onnection regulated 5 v unregulated power agnd reg. load cell cable (6-wires) sense wire sense wire SOC-3000 agnd 68 73 avcc 69 sen- 70 sig - 71 sig + 72 sen + f igure 27: 6-w ire l oad -c ell c onnection
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 77 july, 2002 load cells connected in parallel the SOC-3000 may be connected to up to eight load cells connected in parallel. multiple load cells are required in heavy load applications, such as weigh bridges, that require from two to eight load cells. load cells connected in parallel typically result in lower output impedance, which decreases in direct proportion to the number of load cells. this results in a higher excitation current and higher sensitivity to factors that throw load cells out of balance. the SOC-3000 eliminates this problem with its high common mode rejection ratio (cmrr), which allows the connection of a large number of load cells (up to eight) without losing measurement accuracy. the multiple load-cell connection is shown in figure 28. i mportant the load cells should be matched before connecting them to the SOC-3000 to ensure the same initial offset, span and impedance. this will eliminate error factors that are beyond the control of SOC-3000 electronics. n ote these large weighing platforms may also require a 6-wire interface connection, as described above, on page 75. agnd up to 8 load cells junction box ( * ) output trimming ( * ) zero offset trimming SOC-3000 agnd 68 69 sen- 70 sig - 71 sig + regulated 5 v 73 avcc 72 sen + load cells connection f igure 28: m ultiple l oad -c ell c onnection
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 78 july, 2002 load cell impedance most load cells have output impedance of 350 ohms. however, in power-restricted applications, load cells of higher impedance, typically a 1000-ohm bridge, are used to reduce the cell?s power consumption. the SOC-3000 cmrr minimizes the error resulting from this high bridge impedance and ensures full and accurate performance under this limiting condition. the result is economical power consumption without sacrificing weighing accuracy. keyboard interface the SOC-3000 supports direct connection of a keyboard of up to 64 keys arranged in an 8 8 matrix. the hardware interface with an example of a scale keyboard is shown in figure 29. the keyboard controller (?keyboard controller?, page 31) automatically scans the matrix by asserting a high signal on the output lines (kout 0 to 7) and reading the input lines (kin 0 to 7). the key hardware code, which is the code returned by the keyboard controller when the key is pressed, is shown in figure 12, page 31. the keyboard controller has a programmable anti-bounce mechanism, in which different delays can be programmed to avoid erroneous key activation due to bouncing of the keys. the delay can be set to a discrete value from 4 to 18 milliseconds, in two-millisecond increments. for programming the anti-bounce mechanism, see table 14, page 32. kin7 kin6 kin5 kin4 kin3 kin2 kin1 kin0 82 83 84 1 2 3 4 5 74 75 76 77 78 79 80 8 1 scale keyboard pin # signal kout7 kout6 kout5 kout4 kout3 kout2 kout1 kout0 bsp 7 / 4 1 . q a z 8 * 5 2 0 w s x 9 - 6 3 ? e d c + % = enter r f v f2 f1 f3 f4 t g b f5 f6 f7 f8 esc y h n c m m+ o u j m c e m r p i k l f igure 29: k eyboard i nterface
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 79 july, 2002 lcd display interface the SOC-3000 interface supports lcd displays as follows: ? up to four backplanes, each driving 40 lcd segments ? static, 1/2-bias and 1/3-bias display options ? electro-luminescent (el) lighting control the hardware interface is shown in figure 30. the SOC-3000 is equipped with bias generators with voltage-followers buffers that generate the lcd bias voltages and backplane multiplexing signals. thus, lcd displays can be directly connected to the SOC-3000 without any external component. backplane multiplexer segment inputs 1 2 3 4 18 19 20 21 1 2 22 23 40 61 s40 lcd display (up to 4 backplanes) (up to 40 segments) SOC-3000 pin # signal f igure 30: lcd d isplay i nterface
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 80 july, 2002 led display interface the SOC-3000 interface supports led displays as follows: ? up to 21 digits each comprising eight segments?seven-segment digit plus decimal point (dp) ? three digit groups, weight , price, and total ? automatic hardware refresh mechanism to reduce power consumption the hardware interface is shown in figure 31. the led display is directly connected to the SOC-3000 with the addition of only the led display drivers. digit driver (uln2003) pin 46 pin 52 . . . . . hi- current drivers (dy9953) segment drivers (uln2003) a3-g3,dp3 a2-g2,dp2 a1-g1,dp1 pin 22 pin 45 . . . . . 888 f igure 31: led p arallel d isplay i nterface external interrupt sources external interrupt sources may be connected to the SOC-3000 using the following pins: a. vdet / int0~. b. p3.4 / timer-counter 0 input. c. p3.5 / timer-counter 1 input. using the vdet input: the vdet input is connected to int0 of the 80c51tbo core. in battery-operated equipment this input is connected to the battery voltage divider and used to detect low battery voltage.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 81 july, 2002 other interrupt sources may be connected to this input using open-collector drivers operating in negative logic mode (?0? is active interrupt). a low voltage input triggers the int0. the application software applies a mechanism to determine whether the interrupt was generated by low battery voltage or by other interrupt source. using timer0 and timer1 inputs: SOC-3000 pin #14 is connected to the 80c51 timer 0 input and pin #15 is connected to timer1 input. these inputs may be used for counting or timer operations, or as additional interrupt inputs to the device. using these inputs as interrupt inputs requires that the appropriate timer be set to 0xfe. the next event causes the counter to increase to 0xff and triggers the timer 0 (or timer 1) interrupt. i 2 c-compatible interface the SOC-3000 may supports a 2-wire i 2 c compatible serial interface. the i 2 c-compatible interface shares its pins with the cpu i/o pins (p1.4, p1.5) and is implemented in software. table 40 provides the hardware interface information: t able 40: i 2 c-c ompatible i nterface h ardware i nterface pin# name description 8 sdata serial data i/o pin 9 sclock serial clock pin power saving schemes SOC-3000/i provides several means for power saving for battery-operated systems: a. set the cpu to idle or powerdown operating modes ? see detailed description in the m8051tbo technical specification, power management section. b. disable unused hardware controllers ? by disabling the controller clock via the ?controllers clock enable register (c200h)?, see tables 33 and 34. c. reduce the cpu frequency to minimum while idle by using the frequency controller. the cpu frequency may be increased on the fly to 16mhz when an interrupt or an event occurred. d. switch the power to the load cell using the i/o pins of the soc and an external switch.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 82 july, 2002 grounding and board layout recommendations as with all high-resolution data converters, special attention must be paid to grounding and to the pcb layout of SOC-3000 based designs in order to achieve optimum performance from the analog-to-digital converter. four-layer boards are recommended where the outer layers are ground layers covering the whole surface, and the inner layers are used for routing the signal lines. the same ground plane should be used for both the digital and analog grounds. keep all ground connection as short as possible. make sure that the return paths of the signals are as close as possible to the paths that the currents took to reach their destinations. avoid digital signals flowing under the analog components area. wherever possible, avoid large discontinuities in the ground plane, since they force the return signals to travel on a longer path. an example of correct implementation is routing all signals through the inner layers and keeping the outer layers for ground. if you plans to connect fast logic signals (rise/fall time < 5ns) to any of the SOC-3000 digital inputs, add a series resistor to each relevant line in order to keep rise and fall times longer than 5ns at the SOC-3000 input pins. a value of 100 ? or 200 ? is usually sufficient to prevent high-speed signals from capacitive coupling into the SOC-3000 and affecting the accuracy of the adc.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 83 july, 2002 i n -c ircuit e mulator (ice) s ystem the in-circuit emulator (ice-3000) system provides full emulation of the SOC-3000 device. it includes a plug-in pod that replaces the SOC-3000 device thus enabling full emulation of the device in the target board. it emulates the SOC-3000 device in real-time simplifying the hardware-software integration process. the ice-3000 is composed of 3 elements: a. ds-51 emulator. b. SOC-3000 personality probe. c. windows-based software debugger. the system enables you to access all SOC-3000 device registers and memory locations and debug the application using free run or breakpoints and single step execution control.
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 84 july, 2002
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 85 july, 2002 e xamples of p in c onfiguration p rogramming the following pages show examples of pin configuration programming, as follows: ? example 1 shows a 20-digit lcd display and an 88 keyboard. ? example 2 shows a 16-digit lcd display, an 84 keyboard, 8 output ports and 4 i/o ports. ? example 3 shows a 21-digit led parallel display, an 88 keyboard and 13 output ports. ? example 4 shows the pin programming for all output and i/o ports. example 1: configuring a 20-digit lcd display and an 8x8 keyboard ? 20-digit lcd display support implies allocation of the whole lcd driver output pins to the lcd display, using 4 backplanes and 40 segments. thus, pins 18-61 should be assigned to the lcd controller/driver. ? 8x8 keyboard support implies allocation of the whole keyboard i/o pins to the keyboard controller. thus, pins 1-5 and 74-84 should be assigned to the keyboard controller. table 41 lists the cfr registers affected and their required values. t able 41: e xample 1: 20-d igit lcd d isplay , 88 k eyboard function cfr register address & value port / segment affected pins lcd display c101h = 00h c102h = 00h c103h = 00h c104h = 00h c105h = 00h c106h = 00h c107h = 00h c108h = 00h c109h = 00h c10ah = 00h c10bh = 00h s37 ? s40 s32 ? s36 s28 ? s31 s24 ? s27 s20 ? s23 s16 ? s19 s12 ? s15 s8 ? s11 s4 ? s7 s1 ? s3 bp1 ? bp4 58 ? 61 53 ? 57 49 ? 52 45 ? 48 41 ? 44 37 ? 40 33 ? 36 29 ? 32 25 ? 28 22 ? 24 18 ? 21 keyboard matrix c10dh = ffh c10eh = ffh kin0 ? kin7 kout0 ? kout7 1 ? 5; 82 ? 84 74 ? 81
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 86 july, 2002 example 2: configuring a 16-digit lcd display, an 8x4 keyboard, 8 output and 4 i/o ports ? 16-digit lcd display support implies partial allocation of the lcd driver output pins to the lcd display, using 4 backplanes and 32 segments. thus, pins 18-52 should be assigned to the lcd controller/driver. ? 8x4 keyboard support implies partial allocation of the keyboard i/o pins to the keyboard controller. thus, pins 1-5 and 78-84 should be assigned to the keyboard controller. ? 8 output ports will be implemented using the 8 pins of the lcd driver that are not used for the display. thus, pins 53-61 should be assigned as output ports. ? 4 i/o ports will be implemented using the 4 pins of the keyboard input matrix that are not used by the keyboard. thus, pins 74-77 should be assigned as i/o ports. table 42 lists the cfr registers affected and their required values. t able 42: e xample 2: 16-d igit lcd d isplay , 84 k eyboard , 8 o utput , 4 i/o function cfr register address & value port / segment affected pins lcd display c102h = e8h c103h = 00h c104h = 00h c105h = 00h c106h = 00h c107h = 00h c108h = 00h c109h = 00h c10ah = 00h c10bh = 00h s32 s28 ? s31 s24 ? s27 s20 ? s23 s16 ? s19 s12 ? s15 s8 ? s11 s4 ? s7 s1 ? s3 bp1 ? bp4 53 49 ? 52 45 ? 48 41 ? 44 37 ? 40 33 ? 36 29 ? 32 25 ? 28 22 ? 24 18 ? 21 keyboard matrix c10dh = ffh c10eh = f0h kin0 ? kin7 kout4 ? kout7 1 ? 5; 82 ? 84 78 ? 81 output ports c101h = ffh c102h = e8h p13.0 ? p13.3 p12.1 ? p12.4 58 ?61 54 ? 57 i/o ports c10e = f0h kout4 ? kout7 p14.0 ? p14.3 78 ? 81 74 ? 77
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 87 july, 2002 example 3: configuring a 21-digit led parallel display, an 8x8 keyboard and 13 output ports ? 21-digit led parallel display support implies full allocation of the led parallel display controller output pins to the led parallel display. thus, pins 22-52 should be assigned to the led parallel display controller. ? 8x8 keyboard support implies full allocation of the keyboard i/o pins to the keyboard controller. thus, pins 1-5 and 74-84 should be assigned to the keyboard controller. ? 13 output ports will be implemented using the available output ports available in the asic. thus, pins 53-61 should be assigned as output ports. table 43 lists the cfr registers affected and their required values. t able 43: e xample 3: 21-d igit led d isplay , 88 k eyboard , 13 o utput function cfr register address & value port / segment affected pins led display c103h = 55h c104h = 55h c105h = 55h c106h = 55h c107h = 55h c108h = 55h c109h = 55h c10ah = 15h dig4 ? 7 seg dp3; dig1 - 3 seg d3 ? g3 seg dp2; a3 ? c3 seg d2 ? g2 seg dp1; a2 ? c2 seg d1 ? g1 seg a1 ? c1 49 ? 52 45 ? 48 41 ? 44 37 ? 40 33 ? 36 29 ? 32 25 ? 28 22 ? 24 keyboard matrix c10dh = ffh c10eh = ffh kin0 ? kin7 kout0 ? kout7 1 ? 5; 82 ? 84 74 ? 81 output ports c101h = ffh c102h = eah c10bh = 56h p13.0 ? p13.3 p12.0 ? p12.4 p4.0 ? p4.3 58 ?61 53 ? 57 18 ? 21
cybratech (2000) ltd. SOC-3000/i scale-on-chip ? asic technical specification revision b page 88 july, 2002 example 4: outputs and i/o ports programming ? output ports support implies full allocation of the lcd display controller output pins to the output function. thus, pins 18-61 should be assigned to the output controller. ? i/o ports support implies full assignment of the keyboard controller pins to the i/o ports. thus, pins 1 ? 5 and 74 ? 84 should be assigned to the i/o controller. t able 44: o utput and i/o p orts p rogramming function cfr register address & value port / segment affected pins output ports c101h = ffh c102h = eah c103h = aah c104h = 80h c106h = 2ah c107h = fch c108h = ffh c109h = eah c10ah = 2ah c10bh = 56h p13.0 ? p13.4 p12.0 ? p12.4 p11.0 ? p11.3 p10.0 p9.0 ? p9.2 p8.0 ? p8.3 p7.0 ? p7.3 p6.0 ? p6.3 p5.0 ? p5.2 p4.0 ? p4.3 58 ? 61 53 - 57 49 ? 52 48 37 ? 39 33 ? 36 29 ? 32 25 ? 28 22 ? 24 18 - 21 i/o ports c10dh = 00h c10eh = 00h p15.0 ? p15.7 p14.0 ? p14.7 1 ? 5; 82 - 84 74 - 81

usa tedea-huntleigh incorporated 20630 plummer street chatsworth, california 91311 u.s.a. tel: +1-818-701-2700 fax: +1-818-701-2799 email: sales@tedea-huntleigh.com germany tedea-huntleigh gmbh mmlingweg 18 d-64297 darmstadt-eberstadt germany tel:+49-6151-94460 fax:+49-6151-944640 uk tedea-huntleigh europe ltd. 37 portmanmoor road cardiff cf24 5he united kingdom tel: +44 (0) 29-20460231 fax: +44 (0) 29-20462173 email: sales@tedea-huntleigh.co.uk france seea sa. 16 rue francis vovelle 28000 chartres france tel: +33-2-37-33-31-20 fax: +33-2-37-33-31-29 taiwan integrated solutions ltd. tel: +886-2-2649-7254 fax: +886-2-2649-7253 cybratech (1998) ltd. 5a hazoran st., po box 8381 netanya, 42506 israel tel: +972-9-8638832 fax: +972- 9-8638822 email: info@cybratech.co.il website: www.cybratech.com document order number: SOC-3000-0001-sp

▲Up To Search▲

Price & Availability of SOC-3000

	To Download SOC-3000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .